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e npirion ? power datasheet en5337qi 3a powersoc voltage mode synchronous buck pwm dc- dc converter with integrated inductor description the en5337qi is a power supply on a chip (powe rsoc) dc - dc converter. it integrates mosfet switches, all small - signal circuits, compensation, and the inductor in an advanced 4mm x 7mm qfn package. the en5337qi is specifically designed to meet th e precise voltage and fast transient requirements of present and future high - performance, low - power processor, dsp, fpga, memory boards , and system level applications in distributed power architecture s . advanced circuit techniques, ultra high switching frequency, and very advanced, high - density, integrated circuit and proprietary inductor technology deliver high - quality, ultra compact, non - isolated dc -dc conversion. the altera enpirion solution significantly helps in system design and productivity by offer ing greatly simplified board design, layout and manufacturing requirements. in addition, a reduction in the number of vendors required for the complete power solution helps to enable an overall system cost savings. all altera enpirion products are rohs com pliant and lead - free manufacturing environment compatible . figure 1: total s olution footprint (not to scale) total area features ? integrated inductor, mosfets, controller ? total power solution 75mm 2 ? minimal external c omponents. ? 3a continuous output current capability ? 5mhz operating frequency. switching frequency can be phase locked to an external clock. ? high efficiency, up to 92%. ? wide input voltage range of 2.375v to 5.5v. ? output enable pin and power ok signal. ? progra mmable soft - start time. ? under voltage lockout, over current, short circuit and thermal protection. ? rohs compliant, msl level 3, 260c reflow. applications ? point of load regulation for low - power processors, network processors, dsps, fpgas, and asics ? noise s ensitive applications such as a/v, rf and gbit i/o ? low voltage, distributed power architectures with 2.5v, 3.3v or 5v rails ? computing, networking, dsl, stb, dvr, dtv, ipc ? ripple sensitive applications ? beat frequency sensitive applications figure 2: typical application schematic v out v in 47 f 1206 22 f 1206 vout ena agnd ss pvin avin pgnd ca pgnd ra rb xfb en 5337 qi en5337qi output cap 47uf/1206 040 2 input cap 22uf/1206 ra 0402 ca 0402 rb 0402 soft start cap www.altera.com/enpirion 02638 october 11, 2013 rev g
e n5337qi ordering information part number temp rating (c) package en53 37 qi - 40 to +85 38 - pin qfn t&r EVB-EN5337QI qfn evaluation board pin assignments (top view) figure 3: pin o ut diagram (top view) note: all perimeter pins must be soldered to pcb. pin description pin n am e function 1- 2, 12, 34- 38 nc(sw) no connect ? these pins are internally connected to the common switching node of the internal mosfets. they are not to be electrically connected to any external signal, ground, or voltage. failure to follow this guideline may result in damage to the device. 3- 4, 22- 25 nc no connect ? these pins may be internally connected. do not connect them to each other or to any other electrical signal. failure to follow this guideline may result in device damage. 5- 11 vout regulated converter output. connect these pins to the load , and place output capacitor from these pins and pgnd pins 13 - 15 13- 18 pgnd input/output power ground. connect the se pins to the ground electrode of the input and output filter capacitors. see vout and pvin pin descriptions for more details. 19- 21 pvin input power supply. connect to input power supply. decouple with input capacitor to pgnd pins 16 - 18. 26 sync exte rnal clock input to synchronize internal switching clock to an external signal 27 enable input enable. applying logic high enables the output and initiates a soft - start. applying a logic low disables the output. 28 pok power ok is an open drain transis tor for power system state indication. pok will be logic high when vout is with - 10% to +20% of vout nominal. 29 eaout optional error amplifier output. allows for customization of the control loop response. 30 ss soft - start node. the soft - start capac itor is connected between this pin and agnd. the value of this capacitor determines the startup time. 31 xf b external feedback input. the feedback loop is closed through this pin. a voltage divider at vout is used to set the output voltage. the mid point of the divider is connected to xfb. a phase lead capacitor from this pin to vout is also required to stabilize the loop. 32 agnd analog ground. this is the ground return for the controller. needs to be connected to a quiet ground. 33 avin input power supply for the controller. needs to be connected to input voltage at a quiet point. nc(sw) nc(sw) nc nc v out v out vout vout vout vout vout nc(sw) pgnd pgnd pgnd pgnd pgnd pgnd pvin nc(sw) nc(sw) nc(sw) nc(sw) nc(sw) avin agnd xfb ss eaout pok enable sync en5337qi 3 1 4 2 5 6 23 25 22 24 21 20 38 37 36 35 34 33 28 30 26 27 29 3132 7 8 9 10 11 12 17 15 19 13 14 16 18 nc nc nc nc pvin pvin 2 www.altera.com/enpirion 02638 october 11, 2013 rev g
en5337qi absolute maximum ratings caution: absolute maximum ratings are stress ratings only. functional operation beyond the recommended operating conditions is not implied. str ess beyond the absolute maximum ratings may impair device life. exposure to absolute maximum rated conditions for extended periods may affect device reliability . parameter symbol min m ax units voltages on pvin, avin, vout v in - 0.5 6.0 v voltages on enab le, p ok - 0.5 v in v voltages on xfb, eaout, sync, ss - 0.5 2.5 v storage temperature range t stg - 65 150 c maximum operating junction temperature t j- abs max 150 c reflow temp, 10 sec, msl3 jedec j - std - 020a 260 c esd rating ? user pins (based on hbm) 2000 v esd rating - nc pins (based on hbm) 1000 v esd rating (based on cdm) 500 v recommended operating conditions parameter symbol min m ax units input voltage range v in 2.375 5.5 v output voltage range v out 0.60 v in ? v do ? v output cur rent i load 0 3 a operating junction temperature t j- op - 40 125 c operating ambient temperature t amb - 40 85 c ? v do (drop - out voltage) is defined as (i load x dropout resistance). please see electrical characteristics table. thermal characteristics parameter symbol min typ m ax units thermal shutdown t sd 150 c thermal shutdown hysteresis t sdh 20 c thermal resistance: junction to ambient ( note 1 ) ja 30 c/w thermal resistance: junction to case jc 3 c/w note 1 : based on a four layer copper board and proper thermal design in line with jedec eij/jesd51 s tandards 3 www.altera.com/enpirion 02638 october 11, 2013 rev g
en5337qi electrical characteristics note: v in =5.5v over operating temperature range unless otherwise noted. typical values are at ta = 25c. parameter symbol test conditions min t yp m ax units operating input voltage v in 2.375 5.5 v under voltage lock - out ? v in rising v uvlor voltage above which uvlo is not asserted 2.2 v under voltage lock - out ? v in falling v uvlof voltage below which uvlo is asserted 2.1 v shut - down supply current i s enable=0v 100 a feedback pin voltage v xfb feedback node voltage ? factory setting ? t a = 25 c 0.735 0.75 0.765 v feedback pin input leakage current 1 i xfb xfb pin input leakage current -5 5 na line regulation ? 2.375v v 5.5v ? v out_load 0a i 3a ? v out_temp - 40 c temp 85 c 0.003 %/ c v out rise time t rise measured from when v in 4.7nf c ss 100nf ) c ss x 67 k ? rise time accuracy 1 ? t rise 4.7 nf c ss 100nf - 25 +25 % output drop out voltage resistance 1 v do r do v inmin - v out at full load input to output resistance 250 83 500 167 mv m ? maximum continuous outp ut current i out_max_cont 3 a over current trip level i ocp 4.5 a disable threshold v disable enable pin logic low. 0.0 0.8 v enable threshold v enable enable pin logic high 2.375v v in 5.5v 1.8 v in v enable lock - out time t enlo time for device t o re - enable after a falling edge on enable pin 700 s enable pin input current 1 i enable enable pin has ~80k ? pull down 70 a switching frequency (free running) f sw free running frequency of oscillator 5 mhz external sync clock frequency lock rang e f pll_lock range of sync clock frequency 4.5 5.5 mhz sync input threshold ? low v sync_lo sync clock logic level 0.8 v sync input threshold ? high v sync_hi sync clock logic level 1.8 2.5 v pok threshold pok th output voltage as a fraction of expected output voltage 90 % pok output l ow voltage v pokl with 4ma current sink into pok 0.4 v pok output hi voltage v pokh 2.375v v 5.5v 1 i pokl pok high 1 a note 1 : parameter guaranteed by design 4 www.altera.com/enpirion 02638 october 11, 2013 rev g
en5337qi typical performance characteristics efficiency v in = 3.3v v out (from top to bottom) = 2.5, 1.8, 1.2, 1.0 , 0.75 v efficiency v in = 5.0v v out (from top to bottom) = 3.3, 2.5, 1.8, 1.2, 1.0 , 0.75 v output ripple: v in = 3.3 v, v out = 1.2v , iout = 3a c in = 22 output ripple: v in = 3.3 v, v out = 1.2v , iout = 3a c in = 22 30 40 50 60 70 80 90 0 0.5 1 1.5 2 2.5 3 load (amps) efficiency (%) v in = 5v 20 30 40 50 60 70 80 90 0 0.5 1 1.5 2 2.5 3 load (amps) efficiency (%) 20 mhz bw limit 20 mhz bw limit 500 mhz bw 500 mhz bw 5 www.altera.com/enpirion 02638 october 11, 2013 rev g
en5337qi load transient: v in = 5.0v, v out = 1.2v ch.1: v out , ch. 4: i l oad (slew rate 10a/ s) c in = 22 load transient: v in = 3.3 v, v out = 1.2v ch.1: v out , ch. 4: i l oad (slew rate 10a/ s) c in = 22 power up/down at no load: v in /v out = 5.0v/1.2v , 15nf soft - start capacitor, ch.1: enable, ch. 3 : v out , ch. 4 ; pok power up/down into 0.4 ? drop - out voltage enable lock -o ut time, ch.1: enable, ch. 2: v out 0.000 0.050 0.100 0.150 0.200 0.250 0.300 0 0.5 1 1.5 2 2.5 3 load (amps) v do (v inmin - v out ) 6 www.altera.com/enpirion 02638 october 11, 2013 rev g
en5337qi functional block diagram (+) (-) error amp vout p-drive n-drive uvlo thermal limit current limit soft start pll / sawtooth generator (+) (-) pwm comp pvin enable compensation network voltage reference pgnd xfb eaout ss over voltage power good logic pok eaout sync en5337qi nc(sw) agnd regulated voltage avin figure 4: functional block diagram functional description synchronous buck converter the en5337qi is a synchronous, programmable power supply with integrated power mosfet switches and integrated inductor. the nominal input voltage range is 2.375v to 5.5v. the output voltage is programmed using an external resistor divider network. the control loop is voltage - mode with a type iii compensation network. much of the compensation circuitry is internal to the device. however, a phase lead capacitor is required along with the output voltage feedback resistor divider to complete the type iii compensation netwo rk. the device uses a low - noise pwm topology. up to 3a of continuous output current can be drawn from this converter. the 5mhz switching frequency allows the use of small size input / output capacitors, and realizes a wide loop bandwidth within a small foo t print. protection features: the power supply has the following protection features: ? over - current protection (to protect the ic from excessive load current) ? thermal shutdown with hysteresis. ? under - voltage lockout circuit to disable the converter output wh en the input voltage is less than approximately 2.2v additional f eatures: ? the switching frequency can be phase - locked to an external clock to eliminate or move beat frequency tones out of band. ? soft - start circuit, limiting the in - rush current when the conv erter is initially powered up. the soft start time is programmable with appropriate choice of soft start capacitor value. 7 www.altera.com/enpirion 02638 october 11, 2013 rev g
en5337qi ? power good circuit indicating the output voltage is between 90% and 120% of programmed value as long as the feedback loop is closed. p ower - up /down sequencing during power - up, enable should not be asserted before pvin, and pvin should not be asserted before avin. the pvin should never be powered when avin is off. during power down, the avin should not be powered down before the pvin. ty ing pvin and avin or all three pins (avin, pvin, enable) together during power up or power down meets these requirements. enable operation the enable pin provides a means to enable normal operation or to shut down the device. applying logic high will enable the converter into normal operation. when the enable pin is asserted (high) the device will undergo a normal soft start. a logic low will disable the converter. a logic low will power down the device in a controlled manner and the device is subsequently shut down. the device will remain shut - down for the duration of the enable lockout time ( see electrical characteristics table) . if the enable signal is re- asserted during this time, the device will power up with a normal soft - start at the end of the ena ble lockout time. pre - bias start - up the en5337qi does not support startup into a pre - biased condition. be sure the output capacitors are not charged or the output of the en5337qi is not pre - biased when the en5337qi is first enabled. frequency synchronizati on the switching frequency of the dc/dc converter can be phase - locked to an external clock source to move unwanted beat frequencies out of band. to avail this feature, the clock source should be connected to the sync pin. an activity detector recognizes th e presence of an external clock signal and automatically phase - locks the internal oscillator to this external clock. phase - lock will occur as long as the input clock frequency is in the range of 4.5 to 5.5 mhz. when no clock signal is present, the device reverts to the free running frequency of the internal oscillator. spread spectrum mode the external clock frequency may be swept between 4.5 mhz and 5.5 mhz at repetition rates of up to 10 khz in order to reduce emi frequency components. soft - start operati on soft start is a means to reduce the in - rush current when the device is enabled. the output voltage is ramped up gradually upon start - up. the output rise time is controlled by the choice of soft - start capacitor, which is placed between the ss pin (pin 30) and the agnd pin (pin 32). rise time: t r (c ss * 67k ? ) 25% during start - up of the converter, the reference voltage to the error amplifier is linearly increased to its final level by an internal current source of approximately 10ua. the soft star t capacitor should be between 4.7nf and 100 nf. typical soft - start rise time is ~1ms with ss capacitor value of 15nf. the rise time is measured from when v in v uvlor and enable pin voltage crosses its logic high threshold to when v out reaches its programm ed value. pok operation the pok signal is an open drain signal (requires a pull up resistor to v in or similar voltage) from the converter indicating the output voltage is within the specified range. the pok signal will be logic high (v in ) when the output v oltage is above 90% of programmed v out . if the output voltage goes below this threshold, the pok signal will be a t logic low. over - current protection the current limit function is achieved by sensing the current flowing through the power pfet. when the se nsed current exceeds the over current trip point, both power fets are turned off for the remainder of the switching cycle. if the over - current condition is removed, 8 www.altera.com/enpirion 02638 october 11, 2013 rev g
en5337qi the over - current protection circuit will enable normal pwm operation. if the over - current c ondition persists, the soft start capacitor will gradually discharge causing the output voltage to fall. when the ocp fault is removed, the output voltage will ramp back up to the desired voltage. this circuit is designed to provide high noise immunity. th ermal overload protection thermal shutdown circuit will disable device operation when the junction temperature exceeds approximately 150oc. after a thermal shutdown event, when the junction temperature drops by approx 20oc, the converter will re - start with a normal soft - start. input under -v oltage lock -o ut internal circuits ensure that the converter will not start switching until the input voltage is above the specified minimum voltage. hysteresis, input de - glitch , and output leading edge blanking ensure hi gh noise immunity and prevent false uvlo triggers. compensation the en5337qi uses a type 3 compensation network. a piece of the compensation circuit is the phase lead capacitor c a in figure 5 . this network will provide wide loop bandwidth and excellent transient performance for most applications. it is optimized for use with about 50f of output filter capacitance at the voltage sensing point. additional load decoupling capacitance may be placed beyond the voltage sensing point outside the control loop. voltage mode operation provides high noise immun ity at light load, and low output impedance. in some applications modifications to the compensation may be required. for more information, contact power applications support. application information the en5337qi output voltage is determined by the voltag e presented at the xfb pin. this voltage is set by way of a resistor divider between v out and agnd with the midpoint going to xfb. a phase lead capacitor c a is also required for stabilizing the loop . figure 5 shows the re quired components and the equations to calculate the values. figure 5: v out resistor divider network and compensation capacitor c a input capacitor selection the en5337qi requires between 10uf and 20uf of input capacitance. low - cost, l ow -esr ceramic capacitors should be used as input capacitors for this converter. the dielectric must be x5r or x7r rated. y5v or equivalent dielectric formulations must not be used as these lose too much capacitance with frequency, temperature and bias voltage. in some applications, lower value capacitors are needed in parallel with the larger, capacitors in order to provide high frequency decoupling. recommended input capacitors description mfg p/n 10uf, 10v, 10% x7r, 1206 (1 - 2 capacitors needed) murata g rm31cr71a106ka01l taiyo yuden lmk316b7106kl -t 22uf, 10v, 20% x5r, 1206 (1 capacitor needed) murata grm31cr61a226me19l taiyo yuden lmk316bj226ml - t output capacitor selection the en5337qi has been optimized for use with approximately 50f of output filter capacitance at the voltage sensing point xfb v out r a c a r b )75.0( *75.0 22,150 v vout ra rb pf ca k ra ? = =?= 02638 october 11, 2013 rev g
en5337qi additional load decoupling capacitance may be placed beyond the voltage sensing point outside the control loop . low esr ceramic capaci tors are required with x5r or x7r rated dielectric formulation. y5v or equivalent dielectric formulations must not be used as these lose too much capacitance with frequency, temperature and bias voltage. output ripple voltage is determined by the aggregat e output capacitor impedance. output impedance, denoted as z, is comprised of effective series resistance, esr, and effective series inductance, esl: z = esr + esl placing output capacitors in parallel reduces the impedance and will hence result in lower ripple voltage. n total zzzz 1 ... 111 21 +++= typical ripple voltages output capacitor configuration typical output ripple (mvp - p) (as measured on en5335qi evaluation board) 1 x 47 uf 30 47 uf + 10 uf 15 recommended output capacitors description mfg p/n 47uf , 6.3v, 20% x5 r, 1206 (1 capacitor needed) murata grm31cr60j476me19l taiyo yuden jmk212bj476ml - t 10uf, 6.3v, 10% x5r, 0805 (optional 1 capacitor in parallel with 47uf above) murata grm21br60j106ke 1 9l taiyo yuden jmk 212b j106kg -t power - up sequencing du ring power - up, enable should not be asserted before pvin, and pvin should not be asserted before avin. tying all three pins together meets these requirements. thermal considerations the altera enpirion en5337qi dc -dc converter is packaged in a 7 x 4 x 1 .85mm 38 - pin qfn package. the qfn package is constructed with copper lead frames that have exposed thermal pads. the recommended maximum junction temperature for continuous operation is 125c. continuous operation above 125c will reduce long - term reliabil ity. the device has a thermal overload protection circuit designed to shut it off at an approximate junction temperature value of 150c. the silicon is mounted on a copper thermal pad that is exposed at the bottom of the package. the thermal resistance fro m the silicon to the exposed thermal pad is very low. in order to take advantage of this low resistance, the exposed thermal pad on the package should be soldered directly on to a copper ground pad on the printed circuit board (pcb). the pcb then acts as a heat sink. in order for the pcb to be an effective heat sink, the device thermal pad should be coupled to copper ground planes or special heat sink structures designed into the pcb (refer to the recommendations at the end of this note). the junction tempe rature, t j , is calculated from the ambient temperature, t a , the device power dissipation, p d , and the device junction -to - ambient thermal resistance, ja in c/w :: t j = t a + (p d )( ja ) the junction temperature, t j , can also be expressed in terms of the device case temperature, t c , and the device junction -to - case thermal resistance, jc in c/w, as follows: 10 www.altera.com/enpirion 02638 october 11, 2013 rev g
en5337qi t j = t c + (p d )( jc ) the device case temperature, t c , is the temperature at the center of the exposed thermal pad at the bottom of the package. the device junction -to - ambient and junction-to - case thermal resistances, ja and jc , are shown in the thermal characteristics table on page 3 . the jc is a function of the device and the 38 - pin qfn package design . the ja is a function of jc and the user?s system design parameters that include the thermal effectiveness o f the customer pcb and airflow. the ja value shown in the thermal characteristics table on page 3 is for free convection with the device heat sunk (through the thermal pad) to a copper plated four - layer pc board with a full g round and a full power plane following jedec eij/jesd 51 standards. the ja can be reduced with the use of forced air convection. because of the strong dependence on the thermal effectiveness of the pcb and the system design, the actual ja value will be a function of the specific application. 11 www.altera.com/enpirion 02638 october 11, 2013 rev g
en5337qi layout recommendation figure 6 shows critical components and layer 1 traces of a recommended minimum footprint en 5337 qi layout with enable tied to v in in pwm mode. alternate enable configurations, and other small signal pins need to be connected and routed according to specific customer application. please see the gerber files on the altera website www.altera.com/enpirion for exact dimensions and other layers. please refer to this figure while reading the layout recommendations in this section. recommendation 1: input and output filter capacitors should be placed on the same side of the pcb, and as close to the en 5337 q i package as possible. they should be connected to the device with very short and wide traces. do not use thermal reliefs or spokes when connecting the capacitor pads to the respective nodes. the +v and gnd traces between the capacitors and the en 5337 q i should be as close to each other as possible so that th e gap between the two nodes is minimized, even under the capacitors. recommendation 2: three pgnd pins are dedicated to the input circuit, and three to the output circuit. the slit in figure 6 separating the input and output gnd circuits helps minimize noi se coupling between the converter input and output switching loops. recommendation 3: the system ground plane should be the first layer immediately below the surface layer. this ground plane should be continuous and un - interrupted below the converter and t he input/output capacitors. please see the gerber files on the altera website www.altera.com/enpirion . recommendation 4 : the large thermal pad underneath the component must be connected to the system ground pl ane through as many vias as possible. figure 6 : top pcb layer critical components and copper for minimum footprint the drill diameter of the vias should be 0.33mm , and the vias must have at least 1 oz. copper plating on the inside wall, making the finis hed hole size around 0.20 - 0.26mm . do not use thermal reliefs or spokes to connect the vias to the ground plane. this connection provides the path for heat dissipation from the converter. please see figures: 7, 8, and 9. recommendation 5 : multiple small via s (the same size as the thermal vias discussed in recommendation 4 should be used to connect ground terminal of the input capacitor and output capacitors to the system ground plane. it is preferred to put these vias under the capacitors along the edge of the gnd copper closest to the +v copper. please see figure 6. these vias connect the input/output filter capacitors to the gnd plane, and help reduce parasitic inductances in the input and output current loops. if the vias cannot be placed under c in and c ou t , then put them just outside the capacitors along the gnd slit separating the two components. do not use thermal reliefs or spokes to connect these vias to the ground plane. recommendation 6 : avin is the power supply for the internal small - signal control circuits. it should be connected to the input voltage at a quiet point. in figure 6 this connection is made at the input capacitor close to the v in connection. 12 www.altera.com/enpirion 02638 october 11, 2013 rev g
en5337qi recommendation 7 : the layer 1 metal under the device must not be more than shown in figure 6. see the section regarding exposed metal on bottom of package. as with any switch - mode dc/dc converter, try not to run sensitive signal or control lines underneath the converter package on other layers. recommendation 8: the v out sense point should be just after the last output filter capacitor. keep the sense trace as short as possible in order to avoid noise coupling into the control loop. recommendation 9 : keep r a , c a , and r b close to the vfb pin (see figures 6 and 7). the vfb pin is a high - impedance, sensitive node. keep the trace to this pin as short as possible. whenever possible, connect r b directly to the agnd pin instead of going through the gnd plane. 13 www.altera.com/enpirion 02638 october 11, 2013 rev g
en5337qi design c onsiderations exposed metal on bottom of package lead frames offers many advantages in thermal performance, in reduced electrical lead resistance, and in overall foot print. however, they do require some special considerations. in the assembly process lead frame construction requires that, for mechanical support, some of the lead - frame cantilevers be exposed at the point where wire - bond or internal passives are attached. this results in several small pads being exposed on the bottom of the package. only the large thermal pad and the perimeter pads are to be mechan ically or electrically connected to the pc board. the pcb top layer under the en5337qi should be clear of any metal except for the large thermal pad and the perimeter pads. the ?grayed - out? area in figure 7 represents the area that should be clear of any metal (traces, vias, or planes), on the top layer of the pcb. figure 7: lead - frame e xposed m etal (package bottom view) . grey area highlights exposed metal below whi c h there should not be any metal (traces, vias, or planes) on the top layer of pc b. recommended pcb footprint figure 8 : en5337qi package pcb footprint 14 www.altera.com/enpirion 02638 october 11, 2013 rev g
en5337qi package and mechanical figure 9 : en5337qi package dimensions contact information altera corporation 101 innovation drive san jose, ca 95134 phone: 408 -544-7000 www.altera.com ? 2013 altera corporation ? confi dential. al l ri ghts reserved. alt era, arria, cyclone, enpirion, hardcopy, max, megacore, ni os, quartus and stratix words and logos are trademarks of altera corporation and registered in the u.s. patent and trademark office and in other countries. all other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. altera warrants performance of its semiconductor products to current specifications in accordance with altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by altera. altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. 15 www.altera.com/enpirion 02638 october 11, 2013 rev g

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